The development of the junction field-effect transistor (JFET) dates back to 1952, when the JFET was first proposed by W. Schockley. The n-JFET comprises, in general, an n-type channel layer and a p-type gate formed in the n-type layer from the top. Contact is made to the p-region and the two n-regions at either side of the top gate, resulting in respective gate, source and drain contacts. The p-JFET has a p-type channel layer and an n.sup.+ gate. In the JFET, the depletion region of a p-n junction is used to modulate the cross-sectional area available for current flow. The current is transported by carriers of one polarity only; hence, it is customary to refer to the field-effect transistor as a unipolar device in contrast to the earlier developed bipolar junction transistor which operates through the injection of minority carriers (Physics and Technology of Semiconductor Devices, A. S. Grove, John Wiley & Sons, 1967, p. 243).
Presently, the unipolar m etal oxide semiconductor field effect transistor (MOSFET) is of far greater commercial importance than the JFET. The MOSFET is a type of surface field-effect transistors. In general, the MOSFET has a source and drain region of n-type or p-type material connected by a narrow channel of semiconductor material. A gate is formed above the channel, but is insulated from the semiconductor material by a thin oxide layer (usually SiO.sub.2). The SiO.sub.2 layer is made sufficiently thin that an electrostatic field produced by a bias voltage on the gate penetrates and controls the conductivity of the channel.
Despite the present popularity of MOSFETs, the JFET has inherent advantages over the MOSFET for certain applications. For example, because there is no gate oxide, JFETs are more suitable for high temperature operation than MOSFETs. In MOSFETs, mobile ions in the gate oxide migrate during operation, causing threshold voltage shifts. The migration rate of mobile ions increases exponentially with temperature.
JFETs are also inherently less sensitive to total dose radiation than MOSFETs. In MOSFETs, charge trapping in the gate oxide during irradiation generally produces a large shift in threshold voltage. While this shift can be substantially reduced by using a very thin (10 nm) gate oxide, it appears that a practical upper limit of 10.sup.7 rad (Si) total-dose resistance exists.
From the above discussion, it may be concluded that the thin gate oxide inherent in MOSFETs is a necessary evil. This is not entirely true, since the gate oxide does provide a significant self-alignment advantage over conventionally fabricated JFET devices.
The MOSFETs are generally fabricated in a "self-aligned" manner. The source and drain, which are formed by ion implantation using the polysilicon gate and oxide for masking, are "self-aligned" with respect to the gate. This processing is possible because the gate is isolated from the heavily-doped source and drain by the gate oxide. In contrast, conventionally fabricated JFETs are not "self-aligned". The gate needs to be photolithographically aligned between the source and drain to avoid shorting. In the non-self-aligned structure, the source and drain parasitic resistances can be high, resulting in low transconductance and output driving capability. Therefore, a need exists for a method of fabricating a self-aligned JFET.
Additionally, a need exists for integrated JFET devices capable of being fabricated by simple and reliable processing steps on thin Si films isolated from an Si substrate by a buried insulating layer, i.e., silicon on insulator (SOI) devices. Because the active semiconductor volume of such devices is small and the devices are dielectrically isolated, such SOI devices are less susceptible than bulk silicon devices, both to logic upset and latch-up induced by transient radiation and single-event upset.